Last decade witnessed a growth on developing of IoT architecture models to cope with various challenges and domains requirements. This leads to rapid increasing the number of the connected devices, which means large amount of data are needed to be stored and processed. Form this context, Cloud Computing is emerged as a solution to enable centrally unlimited storage of data and programs with the

Approximations of the fractional-order differentiator and integrator operators s±r are proposed in this work. These approximations target the realization of these operators using standard active filter transfer functions. Hence, circuit implementations in integrated circuit form or in discrete component form are significantly facilitated. Complementary metal-oxide-semiconductor (CMOS) realizations

A new second-order MOS transistor based circuit block approximating the behavior of a fractional-order capacitor is proposed. The circuit is modular and therefore the order of the approximation can be increased by more stages of the same circuit in cascade or in parallel. Simulation results using a TSMC 65nm CMOS technology are provided and show less than 2o of phase error in two decades around

In this paper, the application of the theory of Lissajous figures to the creation of pinched hysteresis loops, considered to be a characteristic of memristive systems, is demonstrated and experimentally verified using designed electronic circuits in the form of an input impedance. The relationship between the Lissajous-based model of the pinched hysteresis loop and a previously reported integrator

In this paper, a new realization of the fractional capacitor (FC) using passive symmetric networks is proposed. A general analysis of the symmetric network that is independent of the internal impedance composition is introduced. Three different internal impedances are utilized in the network to realize the required response of the FC. These three cases are based on either a series RC circuit

This paper introduces a method for extracting the Cole-impedance model parameters using a meta-heuristic optimization technique. The method is based on a single proposed resistor controlled oscillator (SRCO) where the unknown bio-impedance is embedded. At two different oscillation frequencies, the start-up oscillation condition is recorded. Then the corresponding nonlinear equations are solved

This paper proposes an adaptive transmission modulation (ATM) technique for free-space optical (FSO) links over gamma-gamma turbulence channels.The ATM technique provides efficient utilization of the FSO channel capacity for improving spectral efficiency, by adapting the order of the phase-shift keying modulation scheme, according to the channel conditions and the required bit error rate (BER). To

A seamless and fast handover from one cell to another is one of the main goals of long term evolution (LTE). Hence, the decision of handover is a critical part of the design process of handover. Then the selection of handover parameters must be in a careful and optimal way to have an efficient and successful handover. In this paper, a new optimized CoMP handover algorithm (CoMP HO) for LTE network

This paper introduces an FPGA design methodology of a sample and bit permutation speech encryption system. Pipelining method is used to build the proposed system, which can have different number of permutation levels. The security of the system is evaluated using entropy, Mean Squared Error (MSE) and correlation coefficients comparing the different permutation levels. The results demonstrate the

In this paper, we proposed a new technique for designing a dynamic S-box depended on the idea of DNA module and Chaotic system to increase its security. Lorenz chaotic generator is utilized as the chaos part of the proposed design. This design is Tested on the Field Programmable Gate Array (FPGA) for the use of offline speech encryption and decryption in real time. The experimental results are