Publications

Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up

This paper presents a study for general fractional order oscillator based on two port network where two topologies of oscillator structure with two impedances are discussed. The two impedances are chosen to be fractional elements which give four combinations for each topology. The general oscillation frequency, condition and the phase difference between the two oscillatory outputs are deduced in

This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the

This paper presents a generalization of well-known phase shift oscillator based on single CCII into the fractional order domain. The general state matrix, characteristic equation and design equations are presented. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are introduced in terms of the fractional order parameters. These parameters add

In this paper, a general analysis of the generation for all possible fractional order oscillators based on two-port network is presented. Three different two-port network classifications are used with three external single impedances, where two are fractional order capacitors and a resistor. Three possible impedance combinations for each classification are investigated, which give nine possible

In this paper, a generalized fractional-order form of the simulated inductor using a single current feedback operational amplifier (CFOA) and a fractional-order capacitor is introduced. Analytical expression of the equivalent fractionalorder inductor versus the circuit elements is achieved. Moreover, the effect of the parasitic impedance and the non-idealities of the CFOA are investigated

This paper introduces a study to generalize the design of a continuous time filters into the fractional order domain. The study involves inverting and non-inverting filters based on CFOA where three responses are extracted which are high-pass, band-pass and low-pass responses. The proposed study introduces the generalized formulas for the transfer function of each response with different

This paper studies the synchronization of two coupled neurons using Fitzhugh-Nagumo model in the fractional-order domain. In general, studying systems in the fractional-order domain provides a wider scope view of their behavior. When the neuron is generalized into the fractional-order domain, the normal behaviors displayed in the integer case change. Furthermore, two neurons display various

This paper presents a comparative study of four fractional order filters used for edge detection. The noise performance of these filters is analyzed upon the addition of random Gaussian noise, as well as the addition of salt and pepper noise. The peak signal to noise ratio (PSNR) of the detected images is numerically compared. The mean square error (MSE) of the detected images as well as the

Recently, the memristor based relaxation oscillators become an important topic in circuit theory where the reactive elements are replaced by memristor which occupies a very small area. In this paper, a design of memristor-based relaxation oscillator is introduced based on exponential memristor model. Unlike previously published oscillators which were built based on a simple memristor model, the